Hi ALL ,
Hope you all are doing Good,
The Following are the urgently hiring positions with one of ours client . I request all of you to go through the position details , submit suitable profiles to proceed further.
Position 1:
Job Title: Design Verification Engineer – W
Location: San Jose, CA (Remote is fine from USA /Canada)
Job Description:
Skills Required:
Mandatory Experience:
- Writing and maintaining test plans
- Creating and maintaining UVM testbenches
- Created a module testbench from scratch
- Written Cover points, Assertions (SVA) and closed coverage
- Knowledge of standard bus protocols such as AHB, AXI, etc.
Desirable Experience:
- Scripting and test automation for regression
- Experience with PCIe/NVMe and/or ONFI
- Experience with SSD architecture
Education Requirements:
- BS/MS in EE/CE, plus 5+ years of Design Verification experience
- Familiarity with ASIC, Computer and Embedded Systems Architectures
- Excellent oral and written communication skills with people at all levels, a must.
- Team player, with excellent debugging skills
Position 2:
Job Title: Sr Physical Design Engineer
Location: San Jose, CA
Job Description:
Skills Required:
- 7-10+ Yrs of experience in doing hands on physical design for complete flow of Netlist to GDSII
- Preferred Tool experience on Synopsys ICC2, DC, PT, Calibre OR Genus, Innovus, Tempus, Joules and Calibre; working for last 4+ years.
- Strong fundamentals on Physical design including Synthesis, Floorplan, placement, cts, routing, timing closure 7nm, 16nm, 28nm. 5nm geometry will be advantage.
- Sound expertise in TclTk, Perl, Shell scripting. Technically sound & good team player
- Should have worked on consumer SoC with low power experience.
- Overall, he/she need to ensure successful delivery of his block(s) to customers
Must have:
- Synopsys ICC, ICC2, PT-PTSI, DC, OR Cadence Genus, Innovus, Voltus, Joules and Calibre
- Taking care of Physical design issues like Hierarchical design planning,.
- Timing sign off, PnR, Power sign off, ECO execution, Mentor Calibre based LVS-DRC Closure and Sign off).
- Working at Geometry at 65, 45, 28nm,16nm, 7nm and below.
- This job involves working from customer site.
- motivated technical person who wants to grow experience building large ASIC and exposure to work with multi-site team.
Education:
- Bachelor’s Degree in Engineering
Position 3:
Job Title: Senior Engineer (TLM)
Location: Remote (within USA) Ready to work as per CA time
Experience level: 5-10 years
Must have skills
· Hands-on SW development experience
o Fluent in C/C++
o Experience in python o Experience with at least one build flow flow – Make, CMake, Scons, buck,
o Experience with scripting – bash, python
· Modeling experience o Has developed SW models of HW structures o Familiarity w/ SystemC & TLM frameworks o Understanding of modelling technologies – cycle driven, event driven etc
· Able to dive into SW development and set up infra / frameworks / models from ground up
MUST: C/C++, modelling technologies – cycle driven, event driven, Familiarity w/ SystemC & TLM frameworks
Nice to have skills
· HW architecture / microarchitecture experience o Embedded CPU, NOC, memory, queues, caches etc
AI knowledge is a plus Education: BS/MS in Electrical/Computer Engineering
Best Regards
Madan Mohan| Sr. Recruiter
M 973-833-2335 , 425-500-1010 ext: 332
E: madan.m@quadrantresource.com |www.quadrantresource.com
lets connect :https://www.linkedin.com/in/madan-srikaram-988823194/
4034 148th Ave NE, Suite K1C1, Redmond, WA 98052
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