Design Verification Engineer || San Jose, CA – Onsite

• 5+ years of design verification experience
• You enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs.
• You have hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches.
• You are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.
• You thrive in a fast-paced startup environment and can take ownership of projects with minimal direction.
• You collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights.

Strong candidates may also have experience with

• Experience handling vendors and integration of IP/VIP’s
• UVM/System Verilog