Position- ASIC Power Engineer—
Location- CA – Sunnyvale – Hybrid
ASIC Power Engineer to perform power analysis and optimizations in ASIC for Meta’s AR/VR products. Areas of interests includes Machine Learning. Primary languages are Python, tcl and SystemVerilog.
RESPONSIBILITIES
Perform PPA optimization with Fusion compiler.
Perform RTL and netlist level Power analysis
Perform post-processing and scripting on report log files for format conversion, data analysis and information extraction
Setup, run, debug and analyze reports of ASIC flows (Synthesis, PD, Power, Timing)
Implement some blocks at RTL and UPF
Ability to document and communicate clearly
MINIMUM QUALIFICATIONS
10+ Years of experience as an ASIC Power engineer, or CAD Engineer/Physical Design engineer
Experience with power estimation tools and synthesis, some physical design
Knowledge of power trade-offs in design and back-end implementation
Hands-on experience in scripting, data analysis
BS in Electrical Engineering/Computer Science or equivalent experience
PREFERRED QUALIFICATIONS
Synopsys (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence (Joules)
Python, Perl (or similar) scripting and data-post-processing tools
Excel (or Matlab) for model fitting, data visualization and analysis Experience in low power design, tools and methodologies including power intent UPF specifications Silicon Power Characterization Some power profiling experience at IP/SoC level
Important Pointers
– Looking for Power experts, last resume’s only have key words but not tangible experience
– Needs to be able to explain how to optimize and reduce power, not able to speak to their experience
– Need a dedicated power engineer, only generic engineer profiles were submitted, needs to drive power optimization.
– can work the power tools, actively looking into the design and be able to figure out how to optimize the power
– Current candidates had more physical design experience, this should be earlier experience if anything
– Recent roles needs to be Power Optimization
Must-Have Skills
Power Optimization- Experience with Synopsys (DC, ICC, PTPX/PrimePower, VCS, Verdi) and/or Cadence (Joules)
Should know how to use Python, Perl (or similar) scripting and data-post-processing tools
Experience in low power design, tools and methodologies including power intent UPF specifications
Silicon Power Characterization
Nice-to-have Skills
Some power profiling experience at IP/SoC level
Experience with Silicon Power Characterization
Experience with Data analytics and visualization
Prerequisites
Please ensure all resume's are submitted with the completed screening test below as Client will review based on this assessment
1. Can you list all the commands required to run PrimePower, including loading the design, reading the vector, and performing a quality check?
* Read_library
* Read_verilog/netlist
* Read_spef
* Read_sdc
* read_fsdb/read_vcd
* Source namemapping
* Update power
* Report power
2. How do you check the namemapping quality in PrimePower/PTPX?
* Report_switching_activity
3. How can dynamic power be optimized?
* Optimize clock gating efficiency by writing good RTL.
* DVFS
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