Location – Santa Clara, CA
JD:
The ideal candidate should have a BS/MS in Electrical Engineering 8+ years of experience in hands on digital physical design in ASIC/SOC products.
• Experience in Industry standard CAD tools (static timing analysis, parasitic extraction, place and route, IR drop analysis, DRC checks)
• Experience in physical design sign-off high-speed digital circuits
• Experience in floor planning, closing design sign-off with multiple rails/ESDs
• Experience in standard cell based high speed digital design environment
• Experience in integration of analog hard-IPs
• Excellent oral and written communication skills
Thanks
Yogesh Sharma K,
Reveille Technologies, Inc