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Urgent requirement for Design Verification Engineer || Bay Area, CA

Hi,

 

Hope you are doing good!

 

My name is Ashok, working as a Senior Consultant with NeerInfo Solutions Inc… I came across your profile while working on an urgent requirement for one of our clients as a Design Verification Engineer || Bay Area, CA. I feel that your profile and skillsets would be a perfect match for this. Please find the below job description and respond to me with your updated resume if you would be interested and available in the market.

 
Position: Design Verification Engineer
Location: Bay Area, CA
Duration: FTE
 
Job Description

Responsibilities: 

 

  • Must be a quick learner, independent and communicate well. 
  • Knowledge and hands on experience with Verilog, System Verilog , UVM,debugging waveforms 
  • Building a testbench for a medium complexity block using System Verilog and UVM 
  • Writing random tests, directed tests, error tests & performance tests for a block of medium complexity using System Verilog and UVM. 
  • Developing, maintaining and supporting of the UVM verification environment. 
  • Debugging tests with designengineers to deliverfunctionally correct designblocks 
  • OOPS, randomization, constraints, interfaces 
  • Writing & analyzing functional coverage,assertions 
  • Generating and analyzing code coverage & writing waivers 

 

Skills: 

  • SystemVerilog, UVM expertise 
  • Excellent Pythonscripting skills 

·        PCIe or equivalent protocolexperience 

  • 7 years’ experience & above 
  • Self-starter Must have Skills: 

Skills 

Beginner 

Intermediate 

Expert 

SV-UVM 

 

 

Expert 

Coverage Driven 

Verif 

 

 

Expert 

Scripting 

(Python3/Bash/Tcl) 

 

Intermediate 

 

Fixed point 

Arithmetic 

 

Intermediate 

 

Floating Point 

Arithmetic 

 

Intermediate 

 

PCIe 

 

Intermediate 

 

 

 

 

 
 
 
 
 

Ashok Gautam

Senior Consultant

Email: ashok.gautam@neerinfo.com

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