Verification Engineer Santa Clara, CA Onsite, Any visa

Job Title- Verification Engineer

Visa- Any

Duration- 12+ Months

Interview- Virtual

Client Location- Santa Clara, CA Onsite

Role: Job Responsibilities

Background and Meet and Greet: MANDATORY

Job Description:

• Architect and Create verification environments using System-Verilog and Universal verification methodology-UVM IPs and SoCs with embedded CPUs and analog mixed-signal interfaces.

• Develop test plans and coverage metrics from specifications and writing block and chip-level tests.

• Create PERL/Python scripts to automate creating verification environments, tests generation and debugging.

• Failure analysis of Register Transfer Level and Gate simulations and resolve them by working with design engineers.

• Create low power testcases using UPF or CPF to verify the desired power intent of the SoC.

• Work with architects to determine the use-case scenarios to simulate

Key Responsibilities:

Synopsys/Cadence EDA Verifications tools (Preference: 5)

System Verilog/UVM (Preference: 5)

Python (Preference: 3)

Thanks & Regards

Vicky Yadav

Sr. Technical Recruiter

Contact -201-354-2897

Email – vicky.y@wonese.com” style=”border:0px;font:inherit;margin:0px;padding:0px;vertical-align:baseline” target=”_blank”>vicky.y@wonese.com